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Publikationen

Zeige Ergebnisse 31 bis 40 von 14725.
  1. Hans-Georg Fill; Jennifer Horkoff; Peter Fettke; Julius Köppke

    Generative AI and Conceptual Modeling

    In: Oliver Hinz (Hrsg.). Business & Information Systems Engineering (BISE), Vol. 68, Pages 1-5, Springer Nature LINK, Wiesbaden, 2/2026.

  2. Measurement-Driven Adaptive Low-Overhead Implementation of Multi-Controlled Toffoli Gates

    In: International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS-2026), April 27-29, Bratislava, Slovakia, 2026.

  3. Approximated MAGIC-ReRAM Adder Circuits for Low-Latency In-Memory Computing

    In: International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS-2026), April 27-29, Bratislava, Slovakia, 2026.

  4. Fan-In Aware Graph-Based Optimization for MAC-Based In-Memory Computing

    In: Fatemeh Shirinzadeh, Abhoy Kole, Kamalika Datta, Saeideh Shirinzadeh, Rolf Drechsler. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS-2026), April 27-29, Bratislava, Slovakia, 2026.

  5. Spandan Das; Sayak Deb; Khushboo Qayyum; Sallar Ahmadi-Pour; Christoph Lüth; Rolf Drechsler

    Security-Aware Benchmarks for Performance Exploration of CHERI-Enabled Architectures

    In: International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS-2026), April 27-29, Bratislava, Slovakia, 2026.

  6. Recent advances in tracking control of hydrobatic AUVs

    In: at - Automatisierungstechnik, Vol. 74, No. 2, Pages 91-101, De Gruyter, 3/2026.

  7. Automation of Polynomial Formal Verification using Large Language Models

    In: 44th IEEE VLSI Test Symposium (VTS). IEEE VLSI Test Symposium (VTS-2026), April 27-29, Napa, USA, 2026.

  8. LLM-based Generation of High-Level Benchmarks for MVL Designs

    In: IEEE International Symposium on Multiple-Valued Logic. IEEE International Symposium on Multiple-Valued Logic (ISMVL-2026), May 19-21, Sendai, Japan, 2026.

  9. Sajjad Parvin; Frank Sill Torres; Rolf Drechsler

    Integrating Optical Probing Security Evaluation Framework Into ASIC Design Flow

    In: Workshop on Nano Security on Design, Automation and Test in Europe Conference (DATE). Design, Automation & Test in Europe (DATE-2026), April 20-22, Verona, Italy, 2026.

  10. Caroline Dominik; Rolf Drechsler

    Using Virtual Prototypes for Causal Fault Explanation at System Level

    In: 29. Workshop zu Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" (MBMV-2026), March 17-18, Würzburg, Germany, 2026.