Publikation
Extensible and Configurable RISC-V based Virtual Prototype
Vladimir Herdt; Daniel Große; Hoang M. Le; Rolf Drechsler
In: Forum on specification & Design Languages (FDL). Forum on Specification & Design Languages (FDL-2018), September 10-12, München, Germany, 2018.
Zusammenfassung
Internet-of-Things (IoT) opens a new world of possibilities
for both personal and industrial applications. At the
heart of an IoT device, the processor is the core component.
Hence, as an open and free instruction set architecture RISC-V
is gaining huge popularity for IoT. A large ecosystem is available
around RISC-V, including various RTL implementations at one
end and high-speed instruction set simulators (ISSs) at the
other end. These ISSs facilitate functional verification of RTL
implementations as well as early SW development to some extent.
However, being designed predominantly for speed, they can
hardly be extended to support further system-level use cases such
as design space exploration, power/timing/performance validation
or analysis of complex HW/SW interactions.
In this paper, we propose and implement the first RISC-V
based Virtual Prototype (VP) with the goal of filling this gap.
We provide a RISC-V RV32IM core, a PLIC-based interrupt
controller and an essential set of peripherals together with
SW debug capabilities. The VP is designed as extensible and
configurable platform with a generic bus system and implemented
in standard-compliant SystemC and TLM-2.0. The latter point is
very important, since it allows to leverage cutting-edge SystemCbased
modeling techniques needed for the mentioned use cases.
Our VP allows a significantly faster simulation compared to
RTL, while being more accurate than existing ISSs. Finally, our
RISC-V VP is fully open source to help expanding the RISC-V
ecosystem and stimulating further research and development.