Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression

Publikation

Weiyan Zhang, Mehran Goli, Rolf Drechsler

In: 25th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS-2022) April 6-8 Prague Czech Republic 2022.

Abstrakt

RISC-V-based embedded systems are becoming more and more popular in recent years. Performance estimation of embedded software at an early stage of the design process plays an important role in efficient design space exploration and reducing time-to-market constraints. Although several cycleaccurate RISC-V simulators at different levels of abstraction have been proposed, they have an inherently high cost, both for the development of the simulation setting and for obtaining the software performance in terms of the number of cycles through simulation. This results in a significant burden on designers to perform design space exploration. In this paper, we present a novel ML-based approach, enabling designers to fast and accurately estimate the performance of a given embedded software implemented on the RISC-V processor at the early stage of the design process. The proposed approach is evaluated against a real-world cycle-accurate RISC-V Virtual Prototype (VP) using a set of standard benchmarks. Our experiments demonstrate that our approach allows obtaining highlyaccurate performance estimation results in a short execution time. In comparison to the cycle-accurate RISC-V VP model, the proposed approach achieves up to more than 5× faster simulation speed and less than 2.5% prediction error on average.

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VerSys - Eine konsistente Verifikationsplattform zur frühen Softwareentwicklung für RISC-V-basierte Systeme

Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression

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