Publikation

RISC-V Processor Verification with Coverage-guided Aging

Niklas Bruns, Vladimir Herdt, Eyck Jentzsch, Rolf Drechsler

In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV). ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" (MBMV-2022) February 17-18 virtual 2022.

Abstrakt

In this extended abstract we present an efficient approach for processor verification at the Register-Transfer Level (RTL), using a cross-level setting with an Instruction Set Simulator (ISS) as a reference model. We leverage a custom instruction stream generator tailored for RISC-V, which produces one endless instruction stream at runtime. Moreover, we employ a coverage-guided aging concept which ensures a more uniform distribution of the generated instructions by tracking and updating coverage information in the ISS and dynamically providing feedback to the instruction stream generator. Our case study with an industrial pipelined 32 bit RISC-V processor demonstrates the effectiveness of our approach.

Projekte

Deutsches Forschungszentrum für Künstliche Intelligenz
German Research Center for Artificial Intelligence