MircoRV32: An Open Source RISC-V Cross-Level Platform for Education and Research

Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler

In: 2021 IEEE Workshop on Design Automation for CPS and IoT (DESTION 2021). Design Automation for CPS and IoT (DESTION-2021) befindet sich IEEE/ACM CPS-IoT WEEK 2021 May 18 Nashville/Virtual Tennessee United States IEEE 2021.


In this paper we propose µRV32 (MicroRV32) an open source RISC-V platform for education and research. µRV32 integrates several peripherals alongside a 32 bit RISC-V core interconnected with a generic bus system. It supports bare-metal applications as well as the FreeRTOS operating system. Beside an RTL implementation in the modern SpinalHDL language (µRV32 RTL) we also provide a corresponding binary compatible Virtual Prototype (VP) that is implemented in standard compliant SystemC TLM (µRV32 VP). In combination the VP and RTL descriptions pave the way for advanced cross-level methodologies in the RISC-V context. Moreover, based on a readily available open source tool flow, µRV32 RTL can be exported into a Verilog description and simulated with the Verilator tool or synthesized onto an FPGA. The tool flow is very accessible and fully supported under Linux. As part of our experiments we provide a set of ready to use application benchmarks and report execution performance results of µRV32 at the RTL, VP and FPGA level together with a proof-of-concept FPGA synthesis statistic.


Deutsches Forschungszentrum für Künstliche Intelligenz
German Research Center for Artificial Intelligence