MicroRV32: A SpinalHDL based RISC-V Implementation for FPGAs

Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler

In: University Booth at Design, Automation and Test in Europe (DATE). University Booth at Design, Automation and Test in Europe (DATE) (University Booth-2021) befindet sich Design, Automation and Test in Europe (DATE) February 1-5 Grenoble France 2021.


We propose a demonstration of a lightweight RISC-V implementation called MicroRV32 that is suitable for FPGAs. The entire design flow is based on open source tools. The core itself is implemented in the modern Scala-based SpinalHDL hardware description language. For the FPGA flow, the IceStorm suite is utilized. On the iCE40 HX8K FPGA the design requires about 50% of the resources and can be run at a maximum clock frequency of 34.02 MHz. Beside the core, the design also includes basic peripherals and software examples. MicroRV32 is particularly suitable as a lightweight implementation for research and education. The complete design flow can be executed on a Linux system by means of open source tools which makes the platform very accessible.


Deutsches Forschungszentrum für Künstliche Intelligenz
German Research Center for Artificial Intelligence