Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications

Kamalika Datta, Saman Froehlich, Saeideh Shirinzadeh, Dev Narayan, Yadav Indranil Sengupta, Rolf Drechsler

In: IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC-2022) October 3-5 Patras Greece o.A 2022.


Memristor-based crossbar architectures have been explored by researchers for neuromorphic computing, where analog vector-matrix multiplication can be carried out in a single time step. In this paper we explore such architectures for carrying out various arithmetic operations. Since the computations are carried out in analog domain, they are affected by fabrication and performance variability of the manufactured devices. As a result, there can be inherent errors during the computation. However, the architecture can be suitable for approximate computing applications where some errors can be tolerated. We have proposed a method for carrying out arithmetic operations with any multiple of k-bit resolution on the crossbar, for some limited values of k. The fault tolerant capability of the proposed architecture is evaluated through experimentation on benchmark datasets. We also perform case studies to analyze the performance of the approach with particular emphasis on approximate computing. The results of the case studies show that certain applications indeed exhibit fault tolerance in presence of faulty memristors.

German Research Center for Artificial Intelligence
Deutsches Forschungszentrum für Künstliche Intelligenz