Publication

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler

In: Great Lakes Symposium on VLSI (GLSVLSI). ACM Great Lakes Symposium on VLSI (GLSVLSI-2022) June 6-8 Irvine United States 2022.

Abstract

In this paper, we propose a novel simulation-based cross-level approach for processor verification at the Register-Transfer Level (RTL). We leverage state-of-the-art coverage-guided fuzzing techniques from the software domain to generate processor-level input stimuli. An Instruction Set Simulator (ISS) is utilized as a reference model for the RTL processor under test in an efficient co-simulation setting. To further boost the fuzzing effectiveness, we devised custom mutation procedures tailored for the processor verification domain. Our experiments using the popular open-source RISCV based VexRiscv processor demonstrate the effectiveness of our approach in finding intricate bugs at the processor level.

Projekte

German Research Center for Artificial Intelligence
Deutsches Forschungszentrum für Künstliche Intelligenz